The present invention relates to techniques for subsampling or spreading an image.
Bloomberg et al., EP-A 431 961, describe image reduction and enlargement techniques. As shown and described in relation to FIG. 10, specialized hardware can perform a logical operation between vertically adjacent pixelwords and a pairwise reduction of the resulting pixelword. Reduction occurs in two stages: In the first stage, a vertically adjacent pair of pixelwords is read from a first memory, a first logical operation is carried out, and a second logical operation is carried out between the resulting pixelword and a version that is shifted by one bit to provide a processed pixelword with bits of interest in every other bit position. In the second stage, the valid bits are extracted and compressed, and the result is stored in a second memory. The first stage is an array of bit-slice processors. The second stage includes first and second latched transceivers, each half as wide as a pixelword and each having two ports. One port of each transceiver is coupled to the odd bits of a data bus, which correspond to the bits of interest. The other port of the first transceiver is coupled to the lower half of the data bus, and the other port of the second transceiver is coupled to the upper half of the data bus.
Bloomberg et al. describe a 2.times.2 reduction in which a first pair of vertically adjacent pixelwords are read from the first memory onto the data bus and into registers in the first stage. After logical operations, the first stage provides data on the data bus that includes valid bits in the odd bit positions. The odd bits of the data bus are latched into the first latched transceiver. Then a second pair of pixelwords horizontally adjacent to the first pair are processed in the same way in the first stage, and the odd bits of the data bus are latched into the second latched transceiver. The contents of the two transceivers are then read out onto the data bus to obtain a pixelword that represents the reduction of four pixelwords, which is transferred to a second memory. This overall sequence continues until all pixelwords in a pair of rows are processed. Once the pair of rows has been processed, subsequent pairs are similarly processed.
Bloomberg et al. also describe image enlargement by executing the steps in the reverse order. The processor reads a pixelword and sends the left half through the port of the first transceiver that is coupled to the lower half of the data bus. The resulting word is read onto the data bus through the transceiver's other port, with only every other pixel valid, so the processor needs to validate all the pixels using a sequence of shifts and logic operations. The even bits are all 1's. The expanded pixelword, which alternates 1's with valid data, is read into registers in the first stage. After logical operations, the pixelword is written to two vertically adjacent words in an expanded image. The process is repeated for the right half of the pixelword using the second transceiver. The processor expands an entire row one pixelword at a time and an entire image one row at a time.
Bloomberg et al. note at page 14 lines 35-38 that their algorithms lend themselves to parallelism, with many processors independently performing thresholded reduction on parts of an image, such as bands of a given number of scanlines.